Wafer-level package, a method of manufacturing thereof and a method of manufacturing semiconductor devices from such a wafer-level package

ABSTRACT

A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a wafer-level package,a method of manufacturing thereof, and a method of manufacturingsemiconductor devices from such a wafer-level package. The presentinvention particularly relates to an improved wafer-level package to betested by a preliminary test (PT) and a final test (FT), a method ofmanufacturing the wafer-level package, and a method of manufacturingsemiconductor devices using such a wafer-level package.

[0003] Recently, there is a need for more efficient manufacturing andtesting processes of semiconductor devices. In order to achieve this, afull test (including PT and FT) is implemented on an uncut semiconductorwafer before being cut into individual semiconductor devices. As will bedescribed below, the full test has several advantages over the relatedart in which the semiconductor wafer is cut into individualsemiconductor devices and each of the semiconductor devices are testedindividually.

[0004] The advantages include good handling efficiency, a possibility ofsharing certain equipment and reduced space. If the wafer sizes areequal, handling equipment can be shared. Also, it is possible to savespace otherwise taken up as a storage area and/or an installation areawhen accommodating individualized semiconductor devices (LSI chips) incontainers such as a tray.

[0005] For higher density mounting, there is an increasing need for aKGD (Known-Good Die) and a real-chip-size package (a package having thesame size as that of the semiconductor chip). However, with the packagestructure of the semiconductor device of the related art, which does notcorrespond to the KGD or the real-chip-size package, the area of thepackage is greater than that of the semiconductor chip. Therefore, thesemiconductor wafer must be individualized at some point beforepackaging. Thus, with the package structure of the related art, theentire process, that is to say, from a manufacture process to a testprocess, cannot be implemented on the semiconductor wafer.

[0006] However, with the KGD or the real-chip-size package, since thefinal package configuration corresponds to the area of the semiconductorchip, the entire process can be implemented on the semiconductor wafer.Therefore, the above-described advantages can be obtained.

[0007] 2. Description of the Related Art

[0008] Recently, there is an increasing interest in a wafer-levelpackage which is a package structure with which the entire process fromthe manufacturing process to the testing process can be implemented on asemiconductor wafer. The wafer-level package includes a semiconductorwafer provided with a plurality of semiconductor chip circuits with chipterminals, external connection terminals, redistribution tracesconnecting the chip terminals and the external connection terminals, andan insulating material such as a sealing resin. The insulating materialis provided for protecting the semiconductor chip circuits and theredistribution traces. A structure without the insulating material isalso possible.

[0009] The wafer-level package may be used in two differentconfigurations . One is in the form of a wafer (i.e., before being cut)and the other is in form of individual semiconductor devices (i.e.,after cutting into individual semiconductor chip circuits.)

[0010] In the following, the wafer-level package of the above-describedstructure will be described with regard to a test process thereof. Withthe wafer-level package, like that of the semiconductor devices of otherconfigurations, the manufacture process includes a test process. Thetest process generally includes a preliminary test (PT) and a final test(FT).

[0011] The PT is a test implemented before providing the insulatingmaterial. The PT is a general test such as a conduction test of theinterconnections, and thus does not include the operation test of thesemiconductor chip circuit itself. Since the PT is implemented beforeproviding the insulating material, the PT can be implemented using thechip terminals provided on the semiconductor chip circuit.

[0012] The PT is particularly advantageous for the package structure ofthe semiconductor devices of the related art (hereinafter, referred toas a conventional package), which are not designed for the KGD or forthe real-chip-size package. In a manufacture process of the conventionalpackage, the PT is followed by a cutting process (i.e., dicing process)for individualizing the semiconductor wafer into the semiconductordevices. Then, only those semiconductor devices, which were determinedgood in the PT, are provided with the insulating material and undergothe FT. In other words, those semiconductor devices, which weredetermined bad in the PT, are not provided with the insulating materialand also do not undergo the FT. Thus, the manufacture efficiency can beimproved.

[0013] The FT is implemented after providing the insulating material.The FT is a total test including the operation test of the semiconductorchip circuit. Since the FT is implemented after the insulating materialhas been provided, the FT can only be implemented using the externalconnection terminals exposed from the insulating material. In otherwords, the terminals (such as the chip terminals) other than thosegenerally used by the users are not exposed. Therefore, the chipterminals sealed in the insulating material cannot be used in the FT.

[0014] Therefore, in the related art,. the wafer level package is testedby, first, implementing the PT before providing the insulating materialusing the chip terminals which are not yet covered with the insulatingmaterial. After the PT, the insulating material is provided, and thenthe FT is implemented using the external connection terminals exposedfrom the insulating material.

[0015] In the test process of the related art, the object ofimplementing the PT is to improve manufacture efficiency by avoiding theinsulating material being provided on bad semiconductor devices and thusavoiding the FT being implemented thereon. On the contrary, with thewafer-level package, all semiconductor chip circuits, including circuitsof the bad semiconductor devices, are provided with the insulatingmaterial and undergo the FT, so that it is not necessary to implementthe PT before the FT.

[0016] Also, as has been described above, the wafer-level package isused for simplifying the manufacture process by using the semiconductorwafer from the manufacture process to the test process. For furthersimplifying the manufacture process, the PT and the FT, which in therelated art were implemented as two separate tests, can be integratedinto a single test process.

[0017] When the PT and the FT are integrated into a single test process,the integrated test process can be carried out either before providingthe insulating material (i.e., when the PT is implemented in the relatedart) or after providing the insulating material (i.e., when the FT isimplemented in the related art). When the integrated test process isimplemented before providing the insulating material, it is not possibleto detect any failure produced in the semiconductor chip circuit whileproviding the insulating material. Thus, the test process should beimplemented in a later step in the manufacture process of thesemiconductor device.

[0018] On the contrary, when the integrated test process is implementedafter providing the insulating material, only the external connectionterminals exposed from the insulating material may be connected to testequipment (e.g., a semiconductor tester). That is to say, the chipterminals include terminals which do not serve as the externalconnection terminals but can be used for testing the semiconductor chipcircuit (hereinafter referred to as test chip terminals). There is adrawback that the test chip terminals will be covered with theinsulating material, so that the test using the test chip terminalscannot be implemented after providing the insulating material.

[0019] In order to avoid such a drawback, test terminals may be providedin a region of the semiconductor chip circuit region, which terminalsare exposed from the insulating material and are connected to theabove-described test chip terminals. Thus, with such test terminals, alltests including the PT and the FT (full test) can be implemented afterproviding the insulating material.

[0020] However, the test terminals will not be used after the testprocess, and thus become unwanted terminals for the package. Such testterminals provided on the semiconductor chip circuit forming regionresults in an increase in the size of the semiconductor chip circuitforming region due to an area occupied by the test terminals.Accordingly, it is not possible meet the requirement for aminiaturization of the semiconductor device.

[0021] Also, when the test terminals are provided at a position adjacentto the external connection terminals used for operating thesemiconductor chip, the test terminals may also be mistakenly mounted ona mounting board. In such a case, a false operation may occur.Therefore, the test terminals should not remain on the package after theinsulating material has been provided.

[0022] Further, the PT can be omitted (that is to say, all tests can beimplemented in the FT), but as has been described above, not all testchip terminals can be used in the FT. Therefore, tests, which used to beimplemented in the PT only, cannot be implemented. For example, if theRAM and logic circuits are mounted in a mixed manner, a single test ofthe RAM cannot be carried out. At the same time, recently, since a highreliability is required for the semiconductor device, the PT cannot beomitted just for the sake of simplifying the manufacturing process.

[0023] From the above-described reasons, the PT and the FT have not beenintegrated in the related art. First, the PT is implemented, and thenthe insulating material is provided. Finally, the FT is implemented.Therefore, there is a problem that the manufacture process of thewafer-level package is complicated and thus the manufacture efficiencyis decreased and the manufacture cost is increased.

SUMMARY OF THE INVENTION

[0024] Accordingly, it is a general object of the present invention toprovide a wafer-level package, a method of manufacturing thereof, and amethod of manufacturing a semiconductor device from such a wafer-levelpackage which can solve the problems described above.

[0025] It is another and more specific object of the present inventionto provide a wafer-level package, a method of manufacturing thereof, anda method of manufacturing a semiconductor device from such a wafer-levelpackage which can improve a manufacturing efficiency and reduce amanufacturing cost.

[0026] In order to achieve the above objects according to the presentinvention, a wafer-level package includes:

[0027] a semiconductor wafer having at least one semiconductor chipcircuit forming region each including a semiconductor chip circuit and aplurality of chip terminals, the chip terminals including at least onetest chip terminal and at least one non-test chip terminal;

[0028] at least one external connection terminal electrically connectedto the at least one non-test chip terminal;

[0029] at least one redistribution trace provided on the semiconductorwafer, a first end of the redistribution trace being connected to one ofthe test chip terminals and a second end of the redistribution tracebeing extended out to a position offset from the one of the chipterminals;

[0030] at least one testing member provided in an outer region of thesemiconductor chip circuit forming region, the second end of theredistribution trace being connected to the least one testing member;and

[0031] an insulating material covering at least the redistributiontrace, the at least one external connection terminal and the at leastone testing member being exposed from the insulating material.

[0032] With the wafer-level package described above, even when thetesting member is provided, the semiconductor chip circuit formingregion will not become large. Therefore, the size of each individualizedsemiconductor device will be small compared to that of the structure inwhich the testing member is provided in the semiconductor chip circuitforming region.

[0033] Also, the testing member is provided in the outer region of thesemiconductor chip circuit forming region, which outer region is to beremoved upon individualizing into semiconductor devices. Therefore, evenif the testing member is provided on the wafer-level package, theoperating condition of the individualized semiconductor device will notbe altered.

[0034] In order to achieve the above object, a wafer-level semiconductordevice is disclosed, which includes:

[0035] a semiconductor wafer having chip circuit forming regions;

[0036] at least one testing member provided in an outer region of thechip circuit forming regions; and

[0037] a line provided on the semiconductor wafer and connecting the atleast one testing member and a test terminal provided in one of the chipcircuit forming regions.

[0038] It is still another object of the present invention to provide aneasier method of manufacturing the above-described wafer-level package.

[0039] In order to achieve the above object, a method of manufacturing awafer-level package includes the steps of:

[0040] a) preparing a semiconductor wafer having at least onesemiconductor chip circuit forming region each provided with asemiconductor chip circuit and a plurality of chip terminals, at leastone of the chip terminals being a test chip terminal and at least onebeing a non-test chip terminal;

[0041] b) providing a redistribution layer including an insulating filmhaving through holes on the semiconductor wafer and an electricallyconductive film formed on the insulating film, the film being formedinto redistribution traces having a predetermined pattern;

[0042] c) providing external connection terminals and at least onetesting member on the redistribution layer, the at least one testingmember being provided at an outer region of the at least onesemiconductor chip circuit forming region and connected to the test chipterminal via at least one of the redistribution traces;

[0043] d) testing the at least one semiconductor chip circuit using theat least one-testing member; and

[0044] e) providing a sealing resin on the redistribution layer in sucha manner that top parts of the external connection terminals and the atleast one testing member are exposed from the sealing resin.

[0045] With the above-described method, the external connectionterminals and the testing members can be provided simultaneously.Further, the PT and the FT can be implemented simultaneously. Thus, thepackage manufacturing process and the test process can be simplified.

[0046] It is yet another object of the present invention to provide aneasier method of manufacturing at least one semiconductor device usingthe above-described wafer-level package.

[0047] In order to achieve the above-described object, a semiconductordevice manufacturing method includes the steps of:

[0048] a) manufacturing the wafer-level package as described above,

[0049] b) testing the at least one semiconductor chip circuit providedin the at least one semiconductor chip circuit forming region by meansof said at least one testing member; and

[0050] c) after the step b), cutting the wafer-level package along theouter region so as to manufacture at least one individualizedsemiconductor devices.

[0051] With the above-described method, external connection terminalsand the testing member can be provided simultaneously. Further, the PTand the FT can be implemented simultaneously. Thus, the packagemanufacturing process and the test process can be simplified.

[0052] Also, the testing member will be removed when individualizing thesemiconductor devices, so that the operating condition of theindividualized semiconductor device will not be altered.

[0053] It is yet another object of the present invention to provide asemiconductor device which can be manufactured according to a method ofthe present invention.

[0054] In order to achieve the above object, a semiconductor deviceincludes:

[0055] a semiconductor chip;

[0056] a test terminal and a non-test terminal provided to thesemiconductor chip; and

[0057] a line which is connected to the test terminal and extends out ofa circuit forming region.

[0058] Other objects and further features of the present invention willbe apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0059]FIG. 1 is a diagram showing a connection state of a wafer-levelpackage of a first embodiment of the present invention.

[0060]FIG. 2 is a partial sectional view showing the wafer-level packageof the first embodiment of the present invention taken along a brokenline I-I.

[0061]FIG. 3 is a plan view showing the wafer-level package of the firstembodiment of the present invention.

[0062]FIG. 4 is a partial sectional view showing a wafer-level packageof a second embodiment of the present invention.

[0063]FIG. 5 is a diagram showing a connection state of a wafer-levelpackage of a third embodiment of the present invention.

[0064]FIG. 6 is a diagram showing a connection state of a wafer-levelpackage of a fourth embodiment of the present invention.

[0065]FIG. 7 is a diagram showing a connection state of a wafer-levelpackage of a fifth embodiment of the present invention.

[0066]FIG. 8 is a diagram showing a connection state of a wafer-levelpackage of a sixth embodiment of the present invention.

[0067]FIG. 9 is a diagram showing a connection state of a wafer-levelpackage of a seventh embodiment of the present invention.

[0068]FIG. 10 is a diagram showing a connection state of a wafer-levelpackage of an eighth embodiment of the present invention.

[0069]FIG. 11 is a diagram showing a connection state of a wafer-levelpackage of a ninth embodiment of the present invention.

[0070]FIG. 12 is a diagram showing a connection state of a wafer-levelpackage of a tenth embodiment of the present invention.

[0071]FIG. 13 is a plan view showing a wafer-level package of aneleventh embodiment of the present invention.

[0072]FIG. 14 is a diagram showing a connection state of a wafer-levelpackage of a twelfth embodiment of the present invention.

[0073]FIG. 15 is a diagram showing a connection state of a wafer-levelpackage of a thirteenth embodiment of the present invention.

[0074]FIG. 16 is a flowchart showing a method of manufacturing asemiconductor device using a wafer-level package of one embodiment ofthe present invention.

[0075]FIGS. 17A to 17D are cross-sectional diagrams showing a packagemanufacture process of the method of manufacturing a semiconductordevice using a wafer-level package of one embodiment of the presentinvention.

[0076]FIG. 18 is a cross-sectional diagram showing a test process of themethod of manufacturing a semiconductor device using a wafer-levelpackage of one embodiment of the present invention.

[0077]FIG. 19 is a cross-sectional diagram showing a cutting process ofthe method of manufacturing a semiconductor device using a wafer-levelpackage of one embodiment of the present invention.

[0078]FIG. 20 is a partial sectional view showing a wafer-level packageof a fourteenth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] In the following, principles and embodiments of the presentinvention will be described with reference to the accompanying drawings.

[0080] FIGS. 1 to 3 are diagrams showing a wafer-level package 10A of afirst embodiment of the present invention. FIG. 1 is a diagram showing aconnection state of the wafer-level package 10A, FIG. 2 is a diagramshowing a connection state of the wafer-level package 10A, and FIG. 3 isa diagram showing a connection state of the wafer-level package 10A.

[0081] The wafer-level package 10A may be used as an uncut wafer or maybe cut into individualized semiconductor devices 40 (shown in FIG. 19)having respective semiconductor chip circuits.

[0082] As shown in FIG. 2, the wafer-level package 10A includes asemiconductor wafer 11 provided with external connection terminals 14,redistribution traces 15, test terminals 16, and an insulating layer 17(insulating material).

[0083] The semiconductor wafer 11 is, for example, a silicon substrateprovided with a plurality of semiconductor chip circuit forming regions12 (hereinafter referred to as circuit regions). The circuit region 12is provided with a semiconductor chip circuit and a plurality of chipterminals 13 formed thereon. The chip terminals 13 are connected to thesemiconductor chip circuits. Thus, the semiconductor chip circuit willoperate when signals and electrical power are supplied to the chipterminals 13.

[0084] Also, the plurality of chip terminals 13 may be categorized intotwo groups according to their functions. A first group includes chipterminals directly contributing to the operation of the semiconductorchip circuit, and the other group includes chip terminals used only fortesting the semiconductor chip circuit. In the following description,the chip terminals in the latter group (i.e., chip terminals used fortesting the semiconductor chip circuit) will be referred to as test chipterminals 13A. The chip terminals other than the test chip terminals 13Awill be referred to as non-test chip terminals 13B.

[0085] The external connection terminals 14 are terminals used formounting the wafer-level package 10A or the individualized semiconductordevices 40 on a mounting board (not shown). In the present embodiment,the external connection terminals 14 are directly provided on thenon-test chip terminals 13B and are not provided on the test chipterminals 13A. Therefore, in the present embodiment, the externalconnection terminals 14 are provided at positions corresponding to thenon-test chip terminals 13B. The external connection terminals 14 areprovided so as to protrude by a predetermined amount from the uppersurface of the semiconductor wafer 11. The external connection terminals14 may be provided by techniques such as sputtering, deposition andmetal plating.

[0086] The redistribution traces 15 are made of an electricallyconductive layer and are formed into a predetermined pattern on theupper surface of the semiconductor wafer 11. One end of theredistribution trace 15 is connected to the chip terminal 13 (13A),while the other end of the redistribution trace 15 is connected to thetest terminal 16. In the cross-sectional diagram, the redistributiontrace 15 seem to extend to the external connection terminal 14, however,as can be seen in FIG. 1, in fact, the external connection terminal 14is not connected to the redistribution trace 15. Thus, by providing theredistribution traces 15 on the semiconductor wafer 11, the chipterminals 13 can be extended to desired positions on the semiconductorwafer 11. Then, the external connection terminals 14 or the testterminals 16 can be formed at the desired positions.

[0087] Thus, by providing the redistribution traces 15, there is greaterfreedom in the layout of the terminals. That is to say, with theredistribution traces 15, the respective terminals 13 can be pulled outto positions not only within the circuit region 12 but also outside thecircuit region 12. Hereinafter, the region outside the circuit region 12is referred to as an outer region 18.

[0088] In the present embodiment, as has been described above, theexternal connection terminals 14 are directly formed on the non-testchip terminals 13B. Therefore, the redistribution traces 15 extend onlyfrom the test chip terminals 13A. Also, though not shown, an insulatingfilm is provided on the upper part of the circuit region 12, and theredistribution trace 15 is formed on the insulating film. Therefore,even if the redistribution traces 15 are formed on the circuit region12, the redistribution traces 15 and the semiconductor chip circuit willnot be short-circuited.

[0089] The test terminals 16 are used for testing the semiconductor chipcircuit formed in the circuit region 12. The test terminals 16 areprovided so as to protrude by a predetermined amount from the uppersurface of the semiconductor wafer 11. In a similar matter to theexternal connection terminals 14, the test terminals 16 may be providedby techniques such as sputtering, deposition and metal plating.

[0090] Also, as shown in FIG. 2, the test terminals 16 are configuredsuch that the height of the protrusions and shapes thereof are equal tothose of the external connection terminals 14. The test terminals 16are, via the above-described redistribution traces 15, connected to thetest chip terminals 13A provided in the circuit region 12. Therefore,the test terminals 16 are terminals only used for testing thewafer-level package 10A.

[0091] The insulating layer 17 is made of an insulating material, e.g.,SiO₂, having a predetermined thickness. The insulating layer 17 protectsthe semiconductor chip circuit provided in the circuit region 12, thechip terminals 13, and the redistribution traces 15. In the presentembodiment, the insulating layer 17 is provided on the entire surface ofthe semiconductor wafer 11, with the above-described external connectionterminals 14 and the test terminals 16 being exposed (or protruded) fromthe insulating layer 17.

[0092] Therefore, even after providing the insulating layer 17 on thesemiconductor wafer 11, an electrical conduction with the semiconductorchip circuit can be achieved by means of the external connectionterminals 14 and the test terminals 16.

[0093] Now, the position of the test terminals 16 of the wafer-levelpackage 10A of the above-described structure will be described. As hasbeen described above, the test terminals 16 are connected to the testchip terminals 13A via the redistribution traces 15. Also, theredistribution traces 15 can be extended to positions not only withinthe circuit region 12 but also to the outer region 18.

[0094] The present embodiment is characterized in that theredistribution traces 15 are extended out of the circuit region 12 tothe outer region 18, and the test terminals 16 are provided in the outerregion 18. Also, when the wafer-level package 10A is used asindividualized semiconductor devices 40, a cutting (scribing) process isimplemented on the wafer-level package 10A. The test terminals 16 areprovided on the positions to be scribed (i.e., scribe regions). In FIG.3, the scribe regions are indicated by dash-dot lines.

[0095] With the wafer-level package 10A of the present embodiment, eachof the test chip terminals 13A is extended out of the circuit region 12to the outer region 18 by means of the redistribution trace 15. Then, atan end extended out in the outer region 18, the redistribution trace 15is provided with the test terminal 16 exposed from the insulating layer17. Thus, the test terminals 16 can be used even after the insulatinglayer 17 has been provided.

[0096] Thus, since the test can be implemented using both the externalconnection terminals 14 and the test terminals 16, the PT, which wasimplemented before providing the insulating layer 17, and the FT, whichwas implemented after providing the insulating layer 17, can now beimplemented simultaneously. Accordingly, with a simultaneous full test,the test process (manufacture process) can be simplified and themanufacturing cost can be reduced.

[0097] Also, by providing the redistribution traces 15, the testterminals 16 are provided in the outer region 18 (outside the circuitregion 12). Thus, the area of the circuit region 12 will not increaseeven if the test terminals 16 are provided. Therefore, the size of theindividualized semiconductor device 40 can be reduced.

[0098] Further, the outer region 18, in which the test terminals 16 areprovided, is a region to be removed upon individualizing the wafer-levelpackage 10A into the semiconductor devices 40. Therefore, when thesemiconductor devices 40 are individualized, the test terminals 16 willbe removed together with the outer region 18, and will not remain on thesemiconductor device 40. Therefore, even if the test terminals 16 areprovided on the wafer-level package 10A, the operating condition of theindividualized semiconductor device 40 will not be altered.

[0099] Also, in the above-described embodiment, the test terminals 16are provided in the scribe regions (see FIG. 3). However, the testterminals 16 can be provided at positions not only within the scriberegions, but also in other regions in the outer region 18 other than thescribe regions (e.g., peripheral positions of the semiconductor wafer11).

[0100] In the following, a second embodiment of the present embodimentwill be described.

[0101]FIG. 4 is a partial sectional view showing a wafer-level package10B of a second embodiment of the present invention. In FIG. 4,components which are the same as those of the wafer-level package 10A ofthe first embodiment illustrated in FIGS. 1 to 3 are indicated with thesame reference numbers, and detailed explanations thereof are omitted.This also applies to each of the embodiments described with reference toFIGS. 5 to 20.

[0102] In the wafer-level package 10B of the second embodiment, thesemiconductor wafer 11 is provided with a redistribution layer 19. Theredistribution layer 19 is provided with the external connectionterminals 14, the test terminals 16 and a sealing resin 22 (insulatingmaterial).

[0103] The redistribution layer 19 includes the redistribution traces15, an insulating film 20, and through holes 21. The insulating film 20is made of an insulating material, e.g., SiO₂, and is provided with theredistribution traces 15 having a predetermined pattern. Also, theinsulating film 20 is provided with the through holes 21. The chipterminals 13 provided in the circuit region 12 and the redistributiontraces 15 are electrically connected by means of the through holes 21.

[0104] The sealing resin 22 may be an epoxy-type resin, and can beprovided on the entire surface of the semiconductor wafer 11, forexample, by molding. Also, the above-described external connectionterminals 14 and the test terminals 16 penetrate through this sealingresin 22 and protrude upwards, so as to enable an electrical connectionwith an external part. Also, the external connection terminals 14 areconnected to the chip terminals 13 provided in the circuit region 12 bymeans of through holes 21, but such structure is not shown in the figurefor the sake of clarity.

[0105] The wafer-level package 10B of the above structure may alsoachieve the same effect as that of the wafer-level package 10A of thefirst embodiment. Further, in the present embodiment, the sealing resin22 is made of an epoxy-type resin, which is commonly used as the resinpackage material. Therefore, the semiconductor wafer 11 (thesemiconductor chip circuit, the redistribution traces 15, etc) issecurely protected, thus improving the reliability of the wafer-levelpackage 10B. Also, the sealing resin 22 need not be made of theepoxy-type resin, but can also be made of other resin such as polyimide.

[0106] In the following, a third embodiment of the present inventionwill be described.

[0107]FIG. 5 is a diagram showing a connection state of a wafer-levelpackage 10C of a third embodiment of the present invention. Thewafer-level package 10A of the first embodiment described with referenceto FIGS. 1 to 3 relates to a structure in which the external connectionterminals 14 are formed directly on the non-test chip terminals 13B. Onthe contrary, the present embodiment is characterized in that it isprovided with internal redistribution traces 23 inside the circuitregion 12, so that the non-test chip terminals 13B and the externalconnection terminals 14 are provided at mutually offset positions.

[0108] Thus, the positions of the external connection terminals 14 donot necessarily correspond with the positions of the non-test chipterminals 13B. Also, because the non-test chip terminals 13B and theexternal connection terminals 14 are provided at mutually offsetpositions, the circuit structure of the semiconductor chip circuitwithin the circuit region 12 can be designed with greater freedom.

[0109] In the following, a fourth embodiment of the present inventionwill be described.

[0110]FIG. 6 is a diagram showing a connection state of a wafer-levelpackage 10D of a fourth embodiment of the present invention. Thewafer-level package 10D of the present embodiment is characterized inthat a fuse 24 is provided at an intermediate position of one of theredistribution traces 15 extends out to the outer region 18. The fuse 24prevents an excessive power supply between the test chip terminal 13Aand the test terminal 16. One of the test chip terminals 13A is a powersupply terminal and the test terminals 16 are connected to a powersupply line 42.

[0111] For example, when implementing a burn-in test on a wafer-levelpackage, it is often difficult to provide a power supply lineindependently to each semiconductor chip circuit. As in the presentembodiment, by sharing the power supply line 42 between the plurality ofsemiconductor chip circuits, the burn-in test can be implemented at areduced cost.

[0112] However, when sharing the power supply line 42 between theplurality of semiconductor chip circuits, if a semiconductor chipcircuit has bad DC characteristics (power supply short circuit), thereis a risk of burning other semiconductor chip circuits. By providing thefuse 24, even if an excessive power supply occurs due to the presence ofa bad semiconductor chip circuit, the fuse 24 will break so that othernormal semiconductor chip circuits will be prevented from being damaged.

[0113] Further, the fuse 24 will not remain on the semiconductor device40 since the fuse 24 is provided in the outer region 18, and thus isremoved when individualizing into semiconductor devices 40. Therefore,even if the fuse 24 is provided, the operating condition of theindividualized semiconductor device 40 will not be altered.

[0114] In the following, a fifth embodiment of the present inventionwill be described.

[0115]FIG. 7 is a diagram showing a connection state of a wafer-levelpackage 10E of a fifth embodiment of the present invention. Thewafer-level package 10E of the present embodiment is characterized inthat the test terminals 16 provided for respective ones of the pluralityof circuit regions 12 are connected by a common line 25 formed in theexternal area 18.

[0116] With this structure, by supplying test signals to one of the testterminals 16, the test signals can be simultaneously supplied to theplurality of test terminals 16 via the common line 25. Therefore, anumber of interconnections can be reduced. Also, test efficiency isimproved compared to a structure in which respective signals areprovided to each one of the test terminals 16.

[0117] Also, the common line 25 is provided in the outer region 18, andthus is removed when individualizing into semiconductor devices 40.Therefore, even if the common line 25 is provided on the wafer-levelpackage 10E, the operating condition of the individualized semiconductordevice 40 will not be altered.

[0118] In the following, a sixth embodiment of the present inventionwill be described.

[0119]FIG. 8 is a diagram showing a connection state of a wafer-levelpackage 10F of a sixth embodiment of the present invention. Thewafer-level package 10F of the present embodiment is characterized inthat the non-test chip terminals 13B of the plurality of thesemiconductor chip circuits provided on the semiconductor wafer 11 areconnected by joining lines 26. In detail, in the embodiment shown inFIG. 8, the chip terminal 13C provided in the circuit region 12A and thechip terminal 13D provided in the circuit region 12B are connected bythe joining line 26.

[0120] Some of the non-test chip terminals 13B will be used to improvethe test efficiency and reduce the number of interconnections, so thatsuch non-test chip terminals 13B may remain connected during the test.Thus, by connecting such non-test chip terminals 13B (13C, 13D) by thejoining line 26, it is possible to improve the test efficiency andreduce the number of interconnections.

[0121] Also, the joining lines 26 are provided in the outer region 18,and thus are removed when individualizing into semiconductor devices 40.Therefore, even if the joining lines 26 are provided on the wafer-levelpackage 10F, the operating condition of the individualized semiconductordevice 40 will not be altered.

[0122] In the following, a seventh embodiment of the present inventionwill be described.

[0123]FIG. 9 is a diagram showing a connection state of a wafer-levelpackage 10G of a seventh embodiment of the present invention. Thewafer-level package 10G of the present embodiment is characterized inthat the common lines 25 are provided in the outer region 18, and theredistribution traces 15 are connected to these common lines 25. Also, atest pad 27 is provided at a part of the common line 25. The test pad 27is provided so as to be exposed from the insulating layer 17 (or sealingresin 22).

[0124] With the structure described above, the plurality ofredistribution traces 15 corresponding to the plurality of circuitregions 12 are connected via the common lines 25. Thus, by supplyingtest signals to the test pads 27, the test signals can be simultaneouslysupplied to the plurality of semiconductor chip circuits via the commonline 25. Therefore, a number of interconnections can be reduced. Also,since there is no need to provide the test terminal 16 for each of thesemiconductor chip terminals, it is possible to simplify the structureand the manufacturing processes of the wafer-level package 10G.

[0125] In the following, an eighth embodiment of the present inventionwill be described.

[0126]FIG. 10 is a diagram showing a connection state of a wafer-levelpackage 10H of an eighth embodiment of the present invention. Thewafer-level package 10H of the present embodiment is characterized inthat a plurality of units 28, 29 having different functions are providedin the circuit region 12. Also, the redistribution traces 15 areextended out from each one or a combination of the plurality of units28, 29 to the outer region 18. On the end positioned in the outer region18, the redistribution trace 15 is provided with the test terminal 16.

[0127] In detail, in the present embodiment, the circuit region 12 isprovided with a logic part (LOGIC) 28 and a random-access memory part(RAM) 29. The LOGIC 28 and the RAM 29 are connected by internalconnections 30. Also, the LOGIC 28 is provided with chip terminals (notshown) having the external connection terminals 14 connected thereto.The semiconductor device having a mixed structure of units withdifferent properties or functions, such as the RAM and the LOGIC, isreferred to as a system LSI device. Recently, as a result of a higherdensity and higher performance of the semiconductor devices, more systemLSI devices are used. However, it is difficult to individually test theunits provided in the system LSI device.

[0128] This is because these units are interconnected by the internalconnections 30 in the same circuit region 12 so that there may be a unitthat cannot be directly accessed by the external connection terminals14. For example, with the structure of the present embodiment, the LOGIC28 and the RAM 29 are connected via the internal connections 30, and theexternal connection terminals 14 serve as access terminals to the LOGIC28. Thus, the RAM 29 cannot be directly accessed via the externalconnection terminals 14.

[0129] Now, the function of the system LSI device will be described as awhole. The LOGIC 28 accesses the RAM 29 via the internal connections 30so as to acquire and process data in the RAM 29. Then, the thus-obtaineddata is output from the external connection terminals 14. Therefore,with the system LSI of the structure of the related art, it is notpossible to directly access the RAM 29. In other words, the RAM 29cannot be tested individually in the related art.

[0130] However, with the structure of the present embodiment, it is nowpossible to test the RAM 29 individually. The redistribution traces 15are pulled out to the outer region 18 from the RAM 29, and the testterminals 16 are provided on the redistribution trace 15. Thus, the RAM29, which is a unit that is not directly connected to the externalconnection terminals 14, can be tested.

[0131] Accordingly, since it is now possible to test the RAM 29, thereliability of the test can be improved. Also, the redistribution traces15 and the test terminals 16 will be removed when cutting thewafer-level package 10H into individualized semiconductor devices 40.Therefore, the operating condition of the individualized semiconductordevice 40 will not be altered.

[0132] In the following, a ninth embodiment of the present inventionwill be described.

[0133]FIG. 11 is a diagram showing a connection state of a wafer-levelpackage 10I of a ninth embodiment of the present invention. Thewafer-level package 10I of the present embodiment includes a burn-intest circuit 32 (Built-In Self Test: BIST). The redistribution traces 15are extended out from the BIST 32 to the outer region 18. The testterminals 16 are provided on the redistribution traces 15 in the outerregion 18.

[0134] The BIST 32 implements the test on a main circuit part 31, sothat it is possible to read out only the result of the test from thetest chip terminals 13A. However, the test chip terminals 13A serving asinput/output terminals of the BIST 32 are used only in the PT (or cannotnot be used in the FT), since the test chip terminals 13A cannot be leftas the external connection terminals after wafer packaging.

[0135] On the contrary, with the present embodiment, the test chipterminals 13A, serving as the input/output terminals of the BIST 32after wafer packaging, can be accessed via the test terminals 16 and theredistribution traces 15. Thus, a test using the BIST 32 can beimplemented in the FT. Thus, the PT will be not as necessary as it usedto be, so that the test (full test) can be implemented only with the FTand without the PT.

[0136] In the following, a tenth embodiment of the present inventionwill be described.

[0137]FIG. 12 is a diagram showing a connection state of a wafer-levelpackage 10J of a tenth embodiment of the present invention. Thewafer-level package 10J of the present embodiment is characterized inthat a circuit exclusively used for a burn-in test 32A (hereinafterreferred to as a BI circuit 32A) is provided in the outer region 18.

[0138] In detail, the redistribution trace 15 is provided from the testchip terminal 13A in the circuit region 12 to the outer region 18. Theredistribution trace 15 is connected to the BI circuit 32A. As has beendescribed above, the BI circuit 32A and the redistribution trace 15 areprovided in the outer region 18. Also, the test terminal 16 may beprovided directly on the BI circuit 32A.

[0139] Now, a full test on the wafer-level package and the normal wafer(here, the wafer-level package and the normal wafer will be referred toas a wafer) will be described. In the related art, the full test on thewafer was not often implemented before individualizing the wafer intothe semiconductor devices. One of the reasons is that it is difficult toimplement a burn-in test on the uncut semiconductor wafer. In otherwords, with the currently available contactor, it is difficult tocontact all of the plurality of terminals (external connection terminals14 and the test terminals 16) provided on each of the semiconductor chipterminals provided on the wafer. This is also because there are severaltens of thousands of terminals provided on the wafer and thus theterminal pitch is narrow.

[0140] In order to minimize such a problem, an attempt has been made toincorporate the BI circuit 32A into the circuit region 12, and thencontacting a few terminals (burn-in terminals accessing the burn-incircuit). However, with the wafer-level package of the related art inwhich the BI circuit 32A is incorporated within the circuit region 12,the burn-in terminals will, together with the external connectionterminals 14, remain in the semiconductor device 40, thus producing thesame problem as above.

[0141] However, with the structure of the present embodiment, theredistribution traces 15 are pulled out from the BI circuit 32A to theouter region 18. The test terminals 16 serving as the burn-in terminalsare provided on the redistribution traces 15 in the outer region 18, sothat it is possible to access the BI circuit 32A via the test terminals16. Thus, the BI circuit 32A can be used after providing the insulatinglayer 17 (sealing resin 22).

[0142] Accordingly, it is possible to implement a burn-in test on thewafer-level package 10I, so that a test with an increased reliability ispossible. Also, since the test terminals 16 will be removed whenindividualizing into the semiconductor devices 40, the operatingcondition of the individualized semiconductor device 40 will not bealtered.

[0143] In the following, an eleventh embodiment of the present inventionwill be described.

[0144]FIG. 13 is a plan view showing a wafer-level package 10K of aneleventh embodiment of the present invention. The wafer-level package10K of the present embodiment is characterized in that a test historyrecording part 33 (test history storage) is provided in the outer region18 on the semiconductor wafer 11.

[0145] The test history recording part 33 is connected to allsemiconductor chip circuits on the semiconductor wafer 11 viaredistribution traces 35 exclusively used for recording provided in theouter region 18. Also, the test history recording part 33 is providedwith access terminals 34 (input/output terminals).

[0146] The access terminals 34 protrude upwards from the insulatinglayer 17 (sealing resin 22) formed on the semiconductor wafer 11, sothat is possible to access the test history recording part 33 afterproviding the insulating layer 17 (sealing resin 22). By accessing thetest history recording part 33, it is possible to store/retrieve thetest data such as test history and the positions of the badsemiconductor chip circuits.

[0147] With the wafer-level package 10K provided with the insulatinglayer 17 or the sealing resin 22, the whole semiconductor wafer 11 iscovered with the resin (in many cases a black resin). Thus, it isdifficult to implement a visual inspection. Also, since thesemiconductor chip circuits are provided on the semiconductor wafer 11with a high density, it is difficult to imprint characters or codesindicating a vast amount of test history information on the peripheralpart of the wafer-level package 10K.

[0148] However, with the test history recording part 33, a vast amountof test history information of the wafer-level package 10K can be easilywritten in/read out. Thus, efficiency and accuracy of the test can beimproved. Also, since the test history recording part 33 is provided onthe outer region 18, it will be removed when individualizing into thesemiconductor devices 40. Thus, the operating condition of theindividualized semiconductor device 40 will not be altered.

[0149] In the following, a twelfth embodiment of the present inventionwill be described.

[0150]FIG. 14 is a diagram showing a connection state of a wafer-levelpackage 10L of a twelfth embodiment of the present invention. Thewafer-level package 10L of the present embodiment is provided with atest support element 36 for testing the semiconductor chip circuit onthe outer region 18 on the semiconductor wafer 11. Also, theredistribution traces 15 connected to the test chip elements 13Aprovided in the circuit region 12 are connected to the test supportelement 36 via the common line 25.

[0151] The test support element 36 may be an electronic element such asa test LSI circuit or a resistance. With the test support element 36,the efficiency of the wafer-level test can be improved. Also, it isadvantageous when implementing a high-frequency test, since the distancebetween the test chip terminal 13A and the test support element 36 canbe shortened.

[0152] Also, since the test support element 36 and the common line 25are provided in the outer region 18, they will be removed whenindividualizing into the semiconductor devices 40. Thus, the operatingcondition of the individualized semiconductor device 40 will not bealtered.

[0153] In the following, a thirteenth embodiment of the presentinvention will be described.

[0154]FIG. 15 is a diagram showing a connection state of a wafer-levelpackage 10M of a thirteenth embodiment of the present invention. Thewafer-level package 10M of the present embodiment is characterized inthat the test terminals 16 and dummy terminals 38 are provided in anidentification area 37 with a predetermined rule, thus enabling anidentification.

[0155] The identification area 37 is provided in the outer region 18 ofthe semiconductor wafer 11, and the test terminals 16 are connected tothe corresponding circuit region 12 by means of the redistributiontraces 15. Also, the dummy terminal 38 is not connected to theredistribution trace 15, but has the same shape as that of the testterminal 16 and is exposed from the insulating layer 17 (sealing resin22).

[0156] As has been described above, it is difficult to visually inspectthe wafer-level package 10K provided with the insulating layer 17 or thesealing resin 22. However, the test terminals 16 and the dummy terminals38 are arrange with a predetermined rule indicating the characteristics(e.g., index mark, type code, lot identification) of the semiconductorwafer 11 and are exposed from the insulating layer 17 (sealing resin22). Therefore, the semiconductor wafer 11 can be identified by viewingthe positions of the test terminals 16 and the dummy terminals 38, sothat the identification process can be implemented on the wafer-levelpackage 10M, which is not particularly suitable for visual inspection.

[0157] Further, the test terminals 16 and the dummy terminals 38 havingthe identification function are also removed when individualizing intothe semiconductor devices 40. Therefore, the operating condition of theindividualized semiconductor device 40 will not be altered. Also, if theidentification is possible by viewing the positioning of the testterminals 16, it is not always necessary to provide the dummy terminals38.

[0158] In the following, a fourteenth embodiment of the presentinvention will be described.

[0159]FIG. 20 is a cross-sectional view showing a wafer-level package10N of a fourteenth embodiment of the present invention. In wafer-levelpackages 10A to 10M, there is provided the insulating layer 17 or thesealing resin 22 on the redistribution trace 15, whereas the wafer-levelpackage 10N is not provided with the insulating material (insulatinglayer 17, sealing resin 22, etc.) Note that an insulating film isprovided between the semiconductor chip circuit and the redistributiontraces 15.

[0160] With the above-described structure, the redistribution traces 15are always exposed outside, so that the test terminals 16 can be formedon the redistribution traces 15 exposed from the circuit 12. Thus, eachof the semiconductor chip circuits can be tested after the wafer-levelpackage 10N has been manufactured.

[0161] However, as has been described, it is preferable that thatterminals not used by the users are not provided in the circuit region12. Thus, instead of the test terminals 16, flat connection pads capableof being connected to test contacts 41 can be provided in the circuitregion 12 (see FIG. 18). However, in order to achieve a properconnection with the test contact, the connection pad must have a certainarea. Then, with this structure, the area of the circuit region 12 willbecome too large.

[0162] On the contrary, with the wafer-level package 10N of the presentembodiment, the chip terminal 13 used during the test is extended out tothe position outside the circuit region 12 by means of theredistribution trace 15, while providing the test terminal 16 on theredistribution traces 15 thus extended out. Therefore, the circuitregion 12 will not become too large even if the test terminals 16 areprovided. Therefore, compared to the structure where the test terminalsare provided in the circuit region 12, the circuit region 12 can be usedefficiently, and thus when individualized, each of the semiconductordevice 40 will become compact.

[0163] Also, the test terminals 16 are provided at positions to beremoved upon individualizing into semiconductor devices 40, so that thetest terminals 16 will not remain on the individualized semiconductordevices 40. Therefore, even if the test terminals 16 are provided on thewafer-level package 10N, the operating condition of the individualizedsemiconductor device 40 will not be altered.

[0164] In the following, a method of manufacturing the semiconductordevice (hereinafter referred to as a semiconductor device manufacturingmethod) using the wafer-level package of an embodiment of the presentinvention will be described.

[0165] The semiconductor device manufacturing method will be describedwith reference to FIGS. 16 to 19. FIG. 16 is a flowchart showing thesemiconductor device manufacturing method and FIGS. 17A to 19 aredetailed diagrams showing the semiconductor device manufacturing method.

[0166] As shown in FIG. 16, the semiconductor device manufacturingmethod of the present embodiment includes a package manufacturingprocess (step 1), a test process (step 2) and a cutting process (step3).

[0167] In the package manufacturing process (step 1), the wafer-levelpackage 10B of the second embodiment shown in FIG. 4 is manufactured. Inthe test process (step 2), the semiconductor chip circuits provided onthe wafer-level package 10B are tested by means of the test terminals 16and the external connection terminals 14. In the cutting process (step3), the outer region 18 (scribe regions) of the wafer-level package 10Bis cut so as to manufacture the individualized semiconductor devices 40.In the following, each of the processes will be described in detail.

[0168]FIGS. 17A to 17D are diagrams showing the package manufacturingprocess (step 1) for manufacturing the wafer-level package 10B. In orderto manufacture the wafer-level package 10B, first, as shown in FIG. 17A,the semiconductor wafer 11 provided with the circuit regions 12 isprepared.

[0169] Then, as shown in FIG. 17B, the insulating film 20 (SiO₂ film)having a predetermined thickness is provided on the semiconductor wafer11. Also, using a photolithography technique, small holes are formed inthe insulating film 20. Then, an electrically conductive film is formedon the insulating film 20 by plating (or by other thin-film formingtechniques such as sputtering and deposition). Further, theredistribution traces 15 having a predetermined pattern are formed byetching.

[0170] When providing the electrically conductive material, some of theelectrically conductive material will be introduced into theabove-described small holes, so that the through holes 21 are formed.Also, the lower ends of the through holes 21 are electrically connectedto the chip terminals 13 (13A) provided in the circuit region, and theupper ends are electrically connected to the redistribution traces 15.Thus, the redistribution layer 19 is formed on the semiconductor wafer11.

[0171] Then, after providing the redistribution layer 19 as describedabove, the external connection terminals 14 and the test terminals 16are formed as shown in FIG. 17C. As has been described above, theexternal connection terminals 14 and the test terminals 16 may be formedsimultaneously, because their shapes are identical. Therefore, thepresent embodiment is described regarding to a case in which theexternal connection terminals 14 and the test terminals 16 are formedsimultaneously.

[0172] In detail, a mask having openings at positions corresponding tothe external connection terminals 14 and the test terminals 16 is used,and the external connection terminals 14 and the test terminals 16 aregrown by plating (or sputtering or deposition). The heights of theterminals 14, 16 may be adjusted by controlling the plating time. Thus,in the present embodiment, since the external connection terminals 14and the test terminals 16 are formed simultaneously, the manufacturingprocess can be simplified compared to a structure in which the terminals14, 16 are formed in separate steps.

[0173] In the present embodiment, the external connection terminals 14are formed directly on the chip terminals 13B provided on thesemiconductor chip circuit, and the test-terminals 16 are formed on theredistribution traces 15. Also, the test terminals 16 are formed at theposition outside the circuit area 12, i.e., in the outer region 18.

[0174] After the external connection terminals 14 and the test terminals16 are formed in the manner described above, the semiconductor wafer 11is mounted on the mold (not shown) and the resin mold process isimplemented. Thus, as shown in FIG. 17D, the sealing resin 22 is formedon the semiconductor wafer 11. As has been described above, the sealingresin 22 may be made of an epoxy-type resin.

[0175] When forming the sealing resin 22, a molding process isimplemented so that the predetermined top part of the externalconnection terminals 14 and the test terminals 16 are exposed from thesealing resin 22. Therefore, even after the sealing resin 22 (insulatingmaterial) has been provided, the semiconductor chip circuit isaccessible via the external connection terminals 14 and the testterminals 16.

[0176] Thus, by implementing the above-described processes, thewafer-level package 10B is manufactured.

[0177] The package manufacturing process (step 1) is followed by thetest process (step 2). FIG. 18 is a diagram showing the test process.

[0178] In the test process, test contactors 41 connected to asemiconductor device tester (not shown) are brought into contact withthe external connection terminals 14 and the test terminals 16 exposedfrom the sealing resin 22. Then, the PT and the FT, which are carriedout in separate steps in the related art, are implementedsimultaneously.

[0179] That is to say, in the present embodiment, the test terminals 16connected to the test chip terminals 13A can be used after the sealingresin 22 (insulating material) has been provided. Therefore, the testcan be implemented using both the external connection terminals 14 andthe test terminals 16. Thus, the PT, which is implemented beforeproviding the sealing resin 22 in the related art, and the FT, which isimplemented after providing the sealing resin 22 (i.e., a full test),can be implemented simultaneously. Accordingly, the test process can besimplified. Also, the external connection terminals 14 can be providedwith a greater pitch than that for the PT implemented on the wafer.Therefore, it is possible to reduce an accuracy of the contactorsconnected to the external connection terminals 14 during the test. Thus,it is easier to make contact.

[0180] In the embodiment shown in FIG. 18, the contactors connected tothe external connection terminals 14 and the test terminals 16 are shownas probe-type contactors, but contactors of a membrane type may be used.

[0181] When the test history recording part 33 is provided as in thewafer-level package 10K of the eleventh embodiment, shown in FIG. 13,the information obtained from the above-described test is stored in thetest history recording part 33.

[0182] Further, when the wafer-level package 10B is used as an uncutsemiconductor wafer, the cutting process (step 3) described later isomitted and the wafer-level package 10B is mounted on the mountingboard.

[0183] The above-described package manufacturing process (step 1) and atest process (step 2) are followed by the cutting process (step 3). Asshown in FIG. 19, in the cutting process, the outer region 18 is cut andremoved by means of a dicing saw 39. Thus, individualized semiconductordevices 40 are formed.

[0184] The cutting positions (dicing lines) of the dicing saw 39 are atthe outer region 18 as shown by the dash-dot line shown in FIG. 3. Also,after the cutting process by the dicing saw 39, the size of thesemiconductor device 40 viewed from above will be approximately equal tothe size of the circuit region 12. That is to say, the semiconductordevice 40 thus manufactured is a real-chip-size package.

[0185] Since the dicing saw 39 will cut along cutting regions in theouter region 18 and the components (in the present embodiment, theredistribution traces 15, the test terminals 16) provided in the outerregion 18 are removed during the cutting process. According to thestructure of the present embodiment, the manufacturing process can besimplified compared to the structure in which separate processes forremoving the components 15, 16 are provided.

[0186] Also, since the redistribution traces 15 and the test terminals16 will not remain on the individualized semiconductor devices 40, thesemiconductor device 40 can be reduced in size. The presence of theredistribution traces 15 and the test terminals 16 will not alter theoperating condition of the individualized semiconductor device 40.

[0187] The manufacturing method of the present embodiment has beendescribed for the wafer-level package 10B. However, the wafer-levelpackages 10A, 10C to 10M of the first and third to thirteenthembodiments can also be manufactured using generally the samemanufacturing method and the same effects can be achieved.

[0188] Also, with the wafer-level packages 10A, 10C to 10M of eachembodiment, the components provided on the outer region 18 will beremoved in the cutting process. Therefore, the presence of suchcomponents will not alter the operating condition of the individualizedsemiconductor device 40.

[0189] Further, the present invention is not limited to theseembodiments, but variations and modifications may be made withoutdeparting from the scope of the present invention.

[0190] The present application is based on Japanese priority applicationNo. 10-374804 filed on Dec. 28, 1998, the entire contents of which arehereby incorporated by reference.

1-3. (canceled)
 4. A wafer-level package comprising: a semiconductorwafer having at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and an excessive power supply protection element provided insaid outer region and between said test chip terminal and said at leastone testing member.
 5. A wafer-level package comprising: a semiconductorwafer having at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; and an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial, wherein said at least one testing member includes at least onetest terminal corresponding to said least one semiconductor chip circuitforming region, respectively, said test terminal being provided in saidouter region.
 6. A wafer-level package comprising: a semiconductor waferhaving at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; and an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial, wherein said at least one testing member includes a pluralityof test terminals corresponding to a plurality of said semiconductorchip circuit forming regions, respectively, and at least one common lineconnecting said test terminals, said test terminals and said common linebeing provided in said outer region.
 7. A wafer-level packagecomprising: a semiconductor wafer having at least one semiconductor chipcircuit forming region each including a semiconductor chip circuit and aplurality of chip terminals, said chip terminals including at least onetest chip terminal and at least one non-test chip terminal; at least oneexternal connection terminal electrically connected to said at least onenon-test chip terminal; at least one redistribution trace provided onsaid semiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and at least one common line provided in said outer region, aplurality of said redistribution traces extending out of a plurality ofsaid semiconductor chip circuit forming regions being connected to saidcommon line, wherein said at least one testing member includes a testpad provided at a part of said common line and exposed from saidinsulating material.
 8. A wafer-level package comprising: asemiconductor wafer having at least one semiconductor chip circuitforming region each including a semiconductor chip circuit and aplurality of chip terminals, said chip terminals including at least onetest chip terminal and at least one non-test chip terminal; at least oneexternal connection terminal electrically connected to said at least onenon-test chip terminal; at least one redistribution trace provided onsaid semiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and a plurality of units having different functions andprovided within said semiconductor chip circuit forming region, a firstend of said at least one redistribution trace being connected to one of,or combination of, said units, and a second end of said at least oneredistribution trace being connected to said at least one testingmember.
 9. A wafer-level package comprising: a semiconductor waferhaving at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and a test-purpose circuit incorporated in said semiconductorchip circuit forming region, a first end of said at least oneredistribution trace being connected to said test-purpose circuit and asecond end of said at least one redistribution trace being connected tosaid at least one testing member.
 10. A wafer-level package comprising:a semiconductor wafer having at least one semiconductor chip circuitforming region each including a semiconductor chip circuit and aplurality of chip terminals, said chip terminals including at least onetest chip terminal and at least one non-test chip terminal; at least oneexternal connection terminal electrically connected to said at least onenon-test chip terminal; at least one redistribution trace provided onsaid semiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and a test-purpose circuit provided in said outer region,wherein said at least one testing member is provided on the test-purposecircuit or on the redistribution trace extending from the test-purposecircuit.
 11. A wafer-level package comprising: a semiconductor waferhaving at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; a test history recording part provided in said outer regionand connected to said second end of a plurality of said redistributiontraces; and input/output terminals for writing into/reading out fromsaid test history recording part, said input/output terminals beingexposed from said insulating material.
 12. A wafer-level packagecomprising: a semiconductor wafer having at least one semiconductor chipcircuit forming region each including a semiconductor chip circuit and aplurality of chip terminals, said chip terminals including at least onetest chip terminal and at least one non-test chip terminal; at least oneexternal connection terminal electrically connected to said at least onenon-test chip terminal; at least one redistribution trace provided onsaid semiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial; and a common line in said outer region, a plurality of saidredistribution traces extending out of a plurality of said semiconductorchip circuit forming region being connected to said common line, whereinsaid at least one testing member includes a test supporting elementprovided at a part of said common line for testing said semiconductorchip circuit.
 13. A wafer-level package comprising: a semiconductorwafer having at least one semiconductor chip circuit forming region eachincluding a semiconductor chip circuit and a plurality of chipterminals, said chip terminals including at least one test chip terminaland at least one non-test chip terminal; at least one externalconnection terminal electrically connected to said at least one non-testchip terminal; at least one redistribution trace provided on saidsemiconductor wafer, a first end of said redistribution trace beingconnected to one of said test chip terminals and a second end of saidredistribution trace being extended out to a position offset from saidone of said chip terminals; at least one testing member provided in anouter region of said semiconductor chip circuit forming region, saidsecond end of said redistribution trace being connected to said leastone testing member; and an insulating material covering at least saidredistribution trace, said at least one external connection terminal andsaid at least one testing member being exposed from said insulatingmaterial, wherein said at least one testing member includes a pluralityof test terminals provided with a predetermined rule in such a mannerthat said semiconductor wafer can be identified from said positions ofsaid test terminals. 14-18. (canceled)
 19. A wafer-level semiconductordevice comprising: a semiconductor wafer having chip circuit formingregions; at least one testing member provided in an outer region of thechip circuit forming regions; and a line provided on the semiconductorwafer and connecting the at least one testing member and a test terminalprovided in one of the chip circuit forming regions.
 20. A semiconductordevice comprising: a semiconductor chip; a test terminal and a non-testterminal provided to the semiconductor chip; and a line which isconnected to the test terminal and extends out of a circuit formingregion.